1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device which has a metallic silicide layer.
2. Description of the Related Art
In a method for fabricating a semiconductor process, a metallic silicide layer is used for a gate electrode, an active region or conductive line in order to realize lower resistance.
A self-aligned silicide (SALICIDE) method is well known as a method for forming the metallic silicide layer. In the SALICIDE method, first a metallic layer, such as refractory metal is formed on a silicon substrate, and then plural heat treatments are carried out. Generally, a first heat treatment is for forming a metallic silicide in a surface of the substrate by diffusing a material of the metallic layer into the substrate. Other heat treatments are for reducing a resistance of the metallic silicide layer. Thereby, the metallic silicide layer can be formed in predetermined portions in the substrate by a self-aligned method.
Such SALICIDE method is disclosed in Japanese Laid-Open Patent Publication:HEI10-335261, published on Dec. 18, 1998, Japanese Laid-Open Patent Publication:2000-82811, published on Mar. 21, 2000, “Sub-Quarter Micron Titanium Salicide Technology With In Situ Silicidation Using High-Temperature Sputtering” NEC Corporation, 1995 Symposium on VLSI Technology Digest of Technology Papers, p. 57–58 and “The Orientation of Blanket W-CVD on the underlayer Ti/TiN studied by XRD” Toshiba Corporation Semiconductor Company, ADMETA2000:Asian Session, PS-'210, p71–72.
On the other hand, a SOI (Silicon-On-Insulator) structure having a thin single silicon layer formed on an insulating film on a silicon substrate is well known as a structure for realizing lower power consumption.
A technique for applying the SALICIDE method to the SOI structure has been developing in order to realize both a lower resistance and lower power consumption.
A single silicon layer of a fully depleted SOI structure is very thin. Generally, a thickness of such single silicon layer is less than 50 nm. In the case where a thickness of a metallic layer formed on the single silicon layer is 25 nm, a thickness of metallic silicide layers formed in an active region (source and drain regions) becomes 50 nm. That is, the metallic silicide layer in the fully depleted SOI structure might be contacted with the insulating film under the thin single silicon layer without making precisely adjustments to a thickness of the metallic layer formed on the single silicon layer. Such contacted area makes a contact resistance between the metallic silicide layer and the single silicon layer larger since an interface region between the metallic silicide layer and the single silicon layer becomes smaller. Further, in the case where a thickness of the metallic layer is very thicker than that of the single silicon layer, quantity of silicon in the single silicon region is insufficient for reacting with metal in the metallic layer. As a result, voids occur in the active region due to lack of silicon in the single silicon layer.
Therefore, in the case where the SALICIDE method is applied for the SOI structure, a process for forming a thin metallic layer on the active region for forming a thin metallic silicide layer is required.
However, thin wire effect is well known in the conventional silicide process. That is, the narrower a width of the metallic silicide layer becomes, the larger a sheet resistance of the metallic silicide layer becomes. Further, the thin wire effect is remarkable in the thin metallic silicide layer.